Integrated circuits are composed of transistors that comprise various elements, such as flip-flops, ports, and other elements. The transfer of data between these elements must be controlled in order for the integrated circuit to operate in a logical fashion. Clocks are used in an integrated circuit design to provide switching waveforms that control the transfer of data between elements; the elements reached by the timing signal from a particular clock are known as the “clock domain” of that clock. As integrated circuits have gotten more complex, the number of clocks that may be used in a single device has grown dramatically. Some devices may have thousands of clocks.
In many, if not most, design processes, clocks are divided into groups as a quick and convenient way to specify whether clocks are related. In some cases, each clock in a design is compared to each other clock in the design; any two clocks comprise a “clock pair.” Clocks can be either “synchronous,” meaning that the maximum data transfer delay between elements controlled by the two clocks must be met according to their waveform definition, or “asynchronous,” meaning that the clocks are unrelated and thus that the maximum delay between elements controlled by the two clocks does not have any particular maximum delay relationship. Determining when a signal crosses from one clock domain to another is known as a “clock domain crossing” (CDC) analysis.
For synchronous clocks, this ensures that data transmitted by an element that receives a signal from one clock can reliably be received by an element that receives a signal from another related clock. However, if every clock in a design is treated as synchronous, meeting the timing constraints imposed by the various clock specifications will likely be difficult or impossible in most circuits. Since certain electronic design automation (EDA) tools, such as Static Timing Analysis (STA) tools and Physical implementation (PI) tools, will, by default, treat every clock in the design as synchronous unless it is indicated otherwise, defining asynchronous clocks that need not meet such timing constraints is critical.
In addition, it is important to identify clocks that are “physically exclusive,” i.e., that cannot be physically present in the device at the same time. For example, multiple clocks should not be defined on the same clock pin. By contrast, clocks may be “logically exclusive,” where they may physically exist in a circuit at the same time but are not actively used at the same time, for example, if they are multiplexed. However, logically exclusive clocks may still influence each other through crosstalk effects and thus should be considered.
For these reasons, designers typically specify both the timing constraints and any exceptions to synchronous behavior between clocks that they know to be asynchronous. This is often done with a “timing constraint file” which contains definitions of the clock waveforms, as well as any timing exceptions between clock domains and other circuit elements, any “false paths” for which timing need not be considered, and other specifications as necessary or desired.
Previous methods for managing clocks are often adhoc and manually driven, or require the designer to explicitly declare clocks as either asynchronous or synchronous before verifying the exceptions between them. Typically, the designer would insert a number of clock-to-clock timing exceptions (limited by their current understanding), and then find others randomly by an iterative process of using Static Timing Analysis tools to flag violations between asynchronous clocks, and using manual review of thousands to millions of lines of timing specification files to ensure that timing exceptions have not been erroneously inserted between synchronous clock domains.
Other known methods in this field require that any clock transfers determined to be asynchronous should be properly “synchronized” using back-to-back flip-flops. Yet other prior art methods note the necessity of not creating or missing exceptions between asynchronous and synchronous clock pairs, but do little to define how this determination should actually be made.
Modern integrated circuit design can involve hundreds, if not thousands, of independent clocks used to control the design. This number of clocks implies tens of thousands to millions of potential or actual interactions that need to be studied by designers in order to ensure reliable operation of the circuit. In many cases, timing constraints are in flux for much of the design process. Timing exceptions are commonly entered only in response to timing problems, many of which only become noticeable during the place and route portion of the design process. Thus, the CDC analysis often results in extra timing closure iterations, and is not completed and verified until very late in the design process. This may result in delays in finalizing the circuit design as mistakes in the design are repeatedly located and corrected in a time consuming, iterative process.
Thus, it would be useful to identify any timing exceptions between asynchronous and synchronous clocks as early in the implementation schedule as possible in order to ensure proper timing performance of the integrated circuit during the design phase.